The present invention relates in general to semiconductor integrated circuit (IC) process technology, particularly, photolithography used in fabrication of semiconductor ICs, and more particularly to optical proximity correction.
The advent of advanced lithographic techniques and the attempt of chip manufacturers to closely follow Moore's law predicting an exponential growth of number of components on a chip and their shrinkage on the wafer is making the process of designing tools for automating the chip design extremely challenging. The chip is imprinted by means of optical lithographic techniques on the silicon wafer by way of chrome on glassmasks. As the components on the chip become smaller, they are now in the verge of reaching the limits of capacity of the lithographic process.
One of the most common problem of printing integrated circuits on silicon wafers from the mask using lithographic processing is the loss of fidelity of the mask shapes. The dimensions of the wafer shapes are usually much smaller than the wavelength of light that is used in the lithographic processing. The non-linearities associated with this lithographic process of imprinting and the laws of physics associated with light (including diffraction of light waves) makes impressing highly unpredictable. Referring to FIGS. 1A-1B, for example, rectangles 101 on a mask, illustrated in FIG. 1A, are foreshortened into elliptical 102 on the resist, right angles are rounded, and the width of the shapes shrinks, as illustrated in FIG. 1B. In addition to the non-linearity associated with the optical effects, the process of developing after exposing the wafer and the photoactive material (i.e. photoresist, equivalently referred to as resist) thereon also adds to the uncertainty associated with the critical dimensions of the features. Other effects mainly related to the exposure and development effect associated with the resist exist that contribute to the distortions. The wafer shapes get deformed due the diffraction and scattering of light and other related optical and chemical effects of photo-resist materials. The combination of these lithographic processing effects are known as optical proximity effects.
To counter the problem of optical proximity, and increase the fidelity of the wafer printing, mask designers take into account the deformities introduced by the aforementioned lithographic processing effects by intentionally and systematically distorting the original shapes on the mask. The net result of these distortions is that the imprinted shape on the wafer ultimately looks like the target or intended images, satisfying the design rules that were created to achieve the desired yield in chip manufacturing. These methods are generally referred to as optical proximity corrections (OPC). OPC may be performed by simulating the imaging and on-wafer processes, such as etch processes, comparing the simulated image to the target image, and adjusting the mask design so that the simulated image will more closely resemble the target image. This method, also known as model-based OPC (MBOPC), emulates the physical and optical effects that are mostly responsible for shape deformations. At the heart of these methods is a computer simulation program that, given the appropriate optical and physical parameters and the original dimension of the object on the mask, predicts, with a certain degree of accuracy, the printed dimension of the object on the wafer. In the correction phase of the model-based optical proximity correction (MBOPC), the shape on the mask is iteratively modified so that the resulting output closely approximates, within an acceptance criterion, what is desired for the image or imprinted shape on the wafer. This method automatically deforms existing mask shapes to achieve the target dimensions on the wafer.
As target feature size continues to shrink, resolution enhancement techniques (RET) such as alternating phase shift mask (altPSM) or sub-resolution assist features (SRAFs) may be used to print the desired critical dimensions (CD) and provide sufficient lithographic process latitude. RET processes may require heavy overexposure and large etch trim, which can pose a significant challenge to the OPC algorithm, since large discrepancies exist between mask size and actual on-wafer target size. For example, given an initial designed target CD on the mask, the final wafer polysilicon dimension may be shrunk by about 50%. Since the OPC algorithm corrects the mask shapes based on simulated target shapes, the fixed corrections applied to the mask shapes may result in over-correction or under-correction which may converge to a solution only with difficulty, or may not converge at all. In addition, even if a solution is found, there may be large across-chip line width variation (ACLV), and in particular, problems in controlling the gate and polysilicon line widths.
The success of model-based OPC depends on a very accurate simulator that would predict the lithographic processing effects. The simulation of the image at points on the mask is computationally very expensive, and is typically limited to selected points. The simulator predicts the lithographic effect corresponding to selected points on the mask. A conventional OPC algorithm compares the simulation to the target at the selected points, and if the difference exceeds a predefined threshold, the mask shape will be modified, typically by modifying the edge segments on the mask by a fixed amount. This process can be better understood by reference to FIGS. 2A-2F.
For example, FIG. 2A illustrates a prior art target shape 307 that corresponds to the desired shape and size of the final pattern on the wafer. The corresponding mask shape 700 initially is set equal to the target shape. In this example, the target shape 307 is assumed to be a dark feature within the boundary of the shape 307. In the expanded view 201 of a portion of the target and mask shape, the segmentation of the mask shape 700 is shown. A first segment F1 is defined by points 211 and 212, and is connected to a second segment F2 defined by points 212 and 213. The OPC software will typically segment the mask shape 700 and allow each segment to be moved independently in order to create the final corrected mask shape. To determine how to move each segment, the lithography process is simulated along a single cut across the segment. These cuts are called the simulation sites. Here, cut A-A′ is the simulation site across the first segment F1 which intersects the segment at point 215. Cut line B-B′ is the simulation site along second segment F2, intersecting the segment F2 at point 225. By only simulating along a single simulation site per segment, the OPC software is able to simulate the lithography behavior across an entire chip in a reasonable amount of time.
Referring to FIG. 2B, a first step in creating the corrected mask shape is to determine the initial error where the edge of each segment will be printed (based on a simulation) compared to where it is desired to be printed (based on the target layer 307). Initially, the mask shape 700 is assumed to be equivalent to the desired target layer shape 307 and the edge placement error is computed along the simulation sites. The simulated image intensity along the simulation site A-A′ is illustrated in the plot 251, and the plot 252 illustrates the intensity along simulation site B-B′. The printed edge of the feature is the location where the image intensity crosses a threshold intensity 50. The location along line A-A′ where the intensity crosses the threshold 50 is indicated as 216, and similarly, the location where the intensity crosses the threshold 50 is indicated as 226. Initially, the printed edge 216, 226 for both simulation sites fall far inside the target edge 215, 225, respectively, for those sites. This indicates that the mask shape 700 for both segments F1, F2 needs to be moved outward, or to the right for segment F1 and up for segment F2. Since the printed edges 216, 226 fall a large distance from the target edge 215, 225, respectively, the mask edge segments F1, F2 are moved a large distance to try to compensate.
The next step in creating the corrected mask shape is to move the mask edge segments according to the computed errors and then resimulate the edge placements at the simulation sites. Referring to FIG. 2C, the mask edge segment F2 has moved outward past the location of simulation site A-A′. The resimulated image intensity along site A-A′ is illustrated in the plot 251′ and along site B-B′ in the plot 252′. It can be seen that the computed edge 216′ for segment F1 now appears to move far beyond the edge target location 215. This signifies to the OPC algorithm that segment F1 needs to be moved inward or to the left. On the other hand, the edge 226′ for segment F2 is found to be converging on the target edge 225.
FIG. 2D illustrates the mask edges 700″ after the next iteration of moving segments F1 and F2. A notch 705 is beginning to appear at segment F1. The intensities at the simulation sites A-A′ (plot 251″) and B-B′ (plot 252″) are then resimulated and the edge placement errors computed. The edge 226″ for segment F2 has now fully converged on the target edge 225 along simulation site B-B′. However, the placement of the mask edge along the segment F2 remains beyond simulation site A-A′ which is encompassed within the mask shape 700″. Because of that, the printed edge 216″ along simulation site A-A′ is still beyond the target edge 215. This indicates to the OPC algorithm that the mask edge for segment F1 still needs to be moved further to the left.
Thus, the OPC algorithm will move the segment F1 again, as illustrated in FIG. 2E. Again the mask edge 700′″ is moved and now a deep notch 705′ is visible at segment F1. Segment F2 has not moved, as its edge 226′″ has converged to the target edge 225 along simulation site B-B′ as illustrated in plot 252′″. After simulation, the computed edge placement errors according to the OPC algorithm continue to indicate that, despite the large notch 705′ created at segment F1, the printed edge 216′″ is still far beyond the target edge 215. This is a consequence of the mask edge segment F2 being placed beyond simulation site A-A′.
This iterative process will continue without any real progress in reducing the edge placement error at site A-A′. At some point, the OPC software will give up trying to fix this point and will leave the large notch 705″ in place, as in FIG. 2F. The main problem with this solution is that the large notch 705″ at segment F1 can cause a very narrow feature to be printed. By comparing the simulated contour along a cut C-C′ (that was not used for the OPC correction) to the simulated contour along the site A-A′ that was used for the OPC correction, it is apparent that the printed edge 216′″ may fall deep inside the target edge 215, causing a risk of failure. A simulated contour 250 shows the ringing that can occur close to the notch.
The root cause of these errors lies in the large separation D in mask edge 700′″ from target edge 307. This separation D causes some simulation sites to be overrun by the mask edge, resulting in the simulation site not accurately predicting the behavior along the segment.
There is, therefore, a need for a method that can improve the robustness of the OPC correction algorithm, that can improve the OPC algorithm for RET methods such as over exposure and etch trim, and to provide improvements to lithography process robustness and improve ACLV.